One of the major parameters to be considered for a memory is the speed of access in a reading mode, i.e. the possibility of speedily reading the memorized state in a chosen cell. A memory with a large cell capacity has a correspondingly slow access in reading mode. It is therefore necessary to find means to accelerate the reading of large memories.
In particular, one of the reasons for the slowness of access to large memories is the high time constant due to the capacitance the access resistance of the bit lines of the memory. The bit lines are conductors used to transmit the signal representing the information memorized in a cell.
In principle, an entire column of cells is connected to one end and the same bit line, so that the capacitance of a bit line is the sum of several hundreds of individual cell capacities.
For floating-gate transistor memories for example, each individual cell has a high capacitance when viewed from the bit line (the drain-gate capacitance of the floating-gate transistor). The sum of the capacities may become very high.
The access resistance comprises all the resistances in series between a cell to be read and the reading amplifier used to read the signal coming from this cell. These resistances include the contact resistance between metallizations and semiconductor zones, the resistance of the metallizations, the internal source-drain resistance of the selection transistors series-connected in the bit line between the cell and the reading amplifier, etc. These resistances have high values.
The result thereof is that there are necessary limits placed on access speed, since any variation in current or voltage due to the information memorized by the cell will be transmitted with a certain time constant.
To accelerate access to the information elements, the reading of a cell is generally done in two stages: a pre-charging stage and a detection stage (namely the reading stage).
During the pre-charging stage, which is generally set off automatically upon the detection of an address of a cell to be read, a predetermined voltage is applied to a corresponding bit line. This predetermined voltage will correspond to the voltage at which the current of the addressed cell will be measured during the reading stage. For example, the bit line can be precharged to approximately one volt.
During this reading stage, the current needed for the reading is injected into the addressed cell, and the voltage variation at the reading amplifier output is examined.
Since the procedure for accelerating the reading is carried out in two stages, the pre-charging stage should be as short as possible.
It is an aim of the invention to accelerate the pre-charging stage.
The pre-charging circuit most conventionally used (because it is particularly simple) is shown in FIG. 1. It comprises a current-voltage converter CIV connected to the bit line by the series-connected access transistors T1 and T2, which are used for the selection of a particular bit line. The current-voltage converter CIV comprises a servo-control circuit for servo-linking the potential of the bit line to a predetermined pre-charging voltage during a pre-charging stage and, secondly, a circuit for transmitting a signal towards a reading amplifier AL, said signal representing the current that goes through a selected cell during a reading stage.
The access transistors T1 and T2, which are made conductive by addressing signals designating a particular bit line, are used to connect the designated bit line to the current-voltage converter CIV during the reading. They are also used to select a bit line at programming stages during which a high programming voltage Vpp is applied to the selected bit line.
The converter CIV should not, however, receive the high voltage Vpp, and this is why this voltage Vpp is applied in a programming stage to the node between the transistors T1 and T2, the transistor T1 being conductive (to connect Vpp to the bit line) while T2 is off (to isolate the converter CIV from Vpp).
The voltage Vpp is applied only in a programming stage, and a transistor Tp, made conductive during this programming stage by a programming signal PRG, is connected between a voltage source at the potential Vpp and the connecting node A between the transistors T1 and T2.